1. Field of the Invention
The present invention relates to emitter coupled logic (ECL) circuitry which is a bipolar digital semiconductor integrated circuit and, more particularly, to a technique for speeding up the ECL circuitry.
2. Description of the Prior Art
Conventionally, ECL circuitry which is categorized as a kind of bipolar digital semiconductor integrated circuitry and, more specifically, as a non-saturation logic circuit, has been used in a central processing unit of a mainframe computer which requires lightning-quick data processing, or in a high-speed instrument, because the ECL circuitry can operate at a higher speed as compared with other logic circuits even though the ECL circuitry consumes a large amount of power. In general, the ECL circuitry has a pair of differential transistors having emitters connected to each other, and it serves as a balanced differential amplifier which can operate according to a current controlled by a constant-current circuit. The ECL circuitry further comprises an output circuit provided with an output terminal, a load resistor connected between the output terminal and an external power supply, and an emitter-follower transistor having its emitter, which is held in an open state, connected to the output terminal. The ECL circuitry is so constructed as to define the level of its output logic signal according to the level of an input logic signal applied thereto, and increase its capability of driving the load of the output circuit.
Referring now to FIG. 7, there is illustrated a schematic circuit diagram of such the prior art ECL circuitry. In the figure, reference numerals 14 and 15 denote a transistor, 10 and 11 denote a resistor, and 8 denotes a constant-current source Io. These components 14, 15, 10, and 11 construct a differential amplifier. Furthermore, reference numeral 1 denotes an input terminal to which a logic signal Vin is applied. The input terminal 1 is connected to the base of the transistor 14. Reference numeral 2 denotes a terminal to which a constant negative reference voltage Vbb is applied. The terminal 2 is connected to the base of the transistor 15, so that the constant negative voltage Vbb can be used as the reference to be compared with the level of the input logic signal Vin. Furthermore, reference numeral 9 denotes a capacitor which is inevitably parasitic in the input circuit of the ECL circuitry, 16 denotes an emitter-follower output transistor for furnishing an output signal to outside the ECL circuitry, 3 denotes an output terminal connected to the emitter of the output transistor 16, and 12 denotes a load resistor connected between the output terminal 3 and a potential Vtt. These components 16, 3, and 12 construct the output circuit of the ECL circuitry. Furthermore, reference numeral 13 denotes a parasitic capacitor which is inevitably parasitic in the output circuit of the ECL circuitry.
As shown in FIG. 7, the collector of the emitter-follower output transistor 16 is connected to a potential Vcc having a value of ground which is equal to the value of a ground potential used in common with external circuits. Typically, the potential Vcc has a value of zero volt, and the potential or level at any point in each unit of the ECL circuitry is determined or measured, referred to the potential Vcc. In addition, the constant-current source 8 is connected to a negative potential Vee at one end thereof. In general, the potential Vee has a value which is lower than that of the potential Vtt.
When an input signal having a voltage which is higher than that of the reference potential Vbb applied to the terminal 2, i.e., a logic signal at high state is applied to the input terminal 1, a current flowing from the collector to the emitter of the transistor 14 is increased while a current flowing from the collector to the emitter of the transistor 15 is decreased. Accordingly, the collector potential of the transistor 15 is increased, and therefore a current flowing from the base to the emitter of the transistor 16 is increased, so that a low-impedance state is caused between the collector and the emitter of the transistor 16. As a result, a charge is injected into the output terminal 3 connected to the emitter of the output transistor 16 and hence the parasitic capacitor 13 which is parasitic in the output circuit becomes charged, so that the output circuit goes into its high state. The charge time required for charging the parasitic capacitor 13 is determined by the electrical characteristics of the output transistor 16. On the other hand, when an input signal having a voltage which is lower than that of the reference potential Vbb applied to the terminal 2, i.e., a logic signal at low state is applied to the input terminal 1, the current flowing from the collector to the emitter of the transistor 14 is decreased while the current flowing from the collector to the emitter of the transistor 15 is increased. Accordingly, the collector potential of the transistor 15 is decreased, and therefore the current flowing from the base to the emitter of the transistor 16 is decreased, so that a high-impedance state is caused between the collector and the emitter of the output transistor 16. As a result, a charge stored in the parasitic capacitor 13 in the output circuit is discharged by way of the load resistor 12, so that the output circuit and hence the output terminal 3 goes into its low state.
In the ECL circuitry shown in the circuit diagram shown in FIG. 7, the output terminal 3 of the output circuit changes to its high state (or low state) when an input signal at high state (or low state) is injected into the ECL circuitry. Thus, the ECL circuitry can serve as a buffer circuit. By contrast, when applying a logic signal to the terminal 2 instead of the input terminal 1 and applying the reference voltage Vbb to the input terminal 1 instead of the terminal 2, the output terminal 3 of the output circuit changes to its low state (or low state) if the input signal injected into the terminal 2 is at high state (or low state). In this case, the ECL circuitry can serve as an inverter. Furthermore, a circuit having a logic function such as an OR gate or NOR gate can be implemented by incorporating at least one other transistor having its collector and its emitter respectively connected in parallel with the collector and emitter of the transistor 14 into the ECL circuitry. That is, the ECL circuitry can be utilized to implement either a buffer or an inverter by using one of the input terminals 1 and 2 as the reference voltage input terminal. Furthermore, the ECL circuitry can be utilized to implement an OR or NOR gate by adding some transistors to the ECL circuitry.
Even though the ECL circuitry is utilized to implement any one of a buffer, an inverter, or an OR or NOR gate, the parasitic capacitor 13 is inevitably added to the output circuit of the ECL circuitry. For a conventional logic circuit equipped with the prior art ECL circuitry, even though the parasitic capacitor 13 is inevitably added to the output circuit of the ECL circuitry, improvements of the electrical characteristics of the output transistor 16 and design of the logic circuit could increase the operational frequency of the logic circuit without having to reduce the fall time of logic signals, because the rise time of logic signals could be reduced due to the improvements. On the other hand, improvements of techniques of micro scale device have improved the performance of semiconductor integrated circuits, so that semiconductor integrated circuits which can operate at high operational frequencies have been used widely. Recently, designs and prototypes of ECL circuitry which can operate at a clock frequency of 2.5 GHz (i.e., a duration of 400 psec) have been provided.
A matter which has been conventionally considered to be normal becomes a problem in developing ECL circuitry which can stably operate at a clock frequency of 2.5 GHz (i.e., a duration of 400 psec). For example, when the output signal of the ECL circuitry is delivered to the input terminal of other ECL circuitry disposed in the same semiconductor integrated circuit and located at the back of the former ECL circuitry, or when the output signal of the ECL circuitry is delivered to the input terminal of other ECL circuitry disposed in another semiconductor integrated circuit which is adjacent to the semiconductor integrated circuit including the former ECL circuitry, the ECL output signal passes through many paths such as metallic-coated wiring lines, bonding pads, bonding wires, package leads, and a pattern of the printed circuit board. The parasitic capacitor 13 shown in FIG. 7 includes parasitic capacitances included in such the paths and input capacitances included in a circuit at the back of the former ECL circuitry, which connects to the output circuit of the ECL circuitry. Furthermore, the parasitic input capacitor 9 shown in FIG. 7 shows that there can exist a parasitic capacitor which is not negligible at the input terminal 1, which depends on the layout or structure of the logic circuit. Typically, the parasitic capacitor 13 has a 2 to 3 pF of capacitance. Furthermore, most of specifications of ECL circuitry define that the load resistor 12 connected between the output circuit and the potential Vtt has a 50.OMEGA. to 75.OMEGA. of resistance, typically. Since the pattern design of the printed circuit board is built such that the characteristic impedance of the pattern of the circuit board is equal to the resistance value of the load resistor, a change in the design standard of the resistance value of the load resister must be avoided.
When the load resistor 12 has such a defined resistance value, the time constant of the RC circuit including the parasitic capacitor 13 and the load resister 12 is given by the following equation: EQU time constant=50.OMEGA..times.2 to 3 pF=100 to 150 psec.
The time constant exerts an influence upon the time period which elapses when the connection between the collector and the emitter of the output transistor 16 makes a transition from its low-impedance state to its high-impedance state, and the time period which elapses when a charge stored in the parasitic capacitor 13 is discharged by way of the load resister 12 and then the output of the output circuit makes a transition from its high state to its low state. This order of the time constant did not give rise a problem for conventional ECL circuitry which operates at low frequencies. However, when the repetition cycle of the clock signal is 400 psec and the duty factor of the clock signal is 50%, since the duration of each clock pulse at high or low state is 200 psec, the time constant of 100 to 150 psec is not small that it may be ignored. Therefore, a measure to reduce the time constant of the output circuit which determines the discharge time as mentioned above as much as possible has been taken in order to increase the margin of the rise time and fall time of the output with respect to the time constant. The reduction in the time constant can be accomplished by reducing the parasitic capacitance and/or the load resistance. The reduction in the parasitic capacitance 13 can be accomplished by miniaturizing components of the ECL circuitry. Since there is a technical limitation to the reduction in the physical size of components of the ECL circuitry, it is not easy to reduce the parasitic capacitance. On the other hand, it is not desirable to reduce the resistance value of the load resistor 12 because it is defined according to the specifications of the ECL circuitry. However, since the time necessary for charging the parasitic capacitor 13 so as to cause the output of the output circuit to make a low to high transition is determined by the electric characteristics of the output transistor 16, the above problem can be solved by reducing the charge time from the viewpoint of the design of the ECL circuitry.